verilog, openlane, tiny tapeout

motor asic

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a closed-loop motor controller in Verilog, taped out on SkyWater 130 nm silicon

details

Aug 2026 – present

  • Designed a closed-loop motor controller in Verilog and taped it out on SkyWater 130 nm silicon through a multi-project wafer shuttle
  • Implemented control arithmetic in fixed point, closing timing at 50 MHz after synthesis
  • Verified with a self-checking testbench and gate-level simulation, then brought up the returned die on hardware